1. Field of the Invention
The present invention relates to a Vernier delay circuit and, more particularly, to a technology for adjusting a delay time.
2. Description of the Related Art
A time to digital converter (hereinafter, referred to as TDC) is known as a device to convert a time difference that occurs between the timing of transition of a first signal (hereinafter, referred to as a start signal) and the timing of transition of a second signal (stop signal) into a digital value. The scheme using a Vernier delay circuit in a TDC to achieve high time resolution is proposed.
FIG. 1 shows the structure of a TDC 300 where a Vernier delay circuit 200 is used. The TDC 300 comprises a Vernier delay circuit 200 and a priority encoder 100. The Vernier delay circuit 200 receives a start signal Sstart and a stop signal Sstop and produces a thermometer code TC where a change in the bits occurs at a position determined by a time difference. The Vernier delay circuit 200 comprises a first delay circuit 210 and a second delay circuit 220, and a thermometer latch TL0-TLN.
The first delay circuit 210 includes a total of N first delay elements D1 connected to form multiple stages. The circuit 210 provides a delay of a first predetermined amount t1 to the start signal Sstart in each stage and outputs a total of (N+1) delayed start signals SA0-SAN delayed by different amounts. Similarly, the second delay circuit 220 includes a total of N first delay elements D2 connected to form multiple stages. The circuit 220 provides a delay of a second predetermined amount t2 to the stop signal Sstop in each stage and outputs a total of (N+1) delayed stop signals SB0-SBN delayed by different amounts.
The first predetermined amount t1 of delay is set to be longer than the second predetermined amount t2. The time difference between the start signal Sstart and the stop signal Sstop is decreased by Δt=(t1−t2) as the signals pass through a delay element of each stage in the first delay circuit 210 and the second delay circuit 220. Given that the initial time difference between the start signal Sstart and the stop signal Sstop is τ, reversal of timing of the edges of the two signals occurs when the signals have passed a total of (τ/Δt) stages of delay elements.
The thermometer latch TLj in the j-th stage (0≦j≦N) latches the delayed stop signal SBj output from the j-th stage when the delayed start signal SAj output from the j-th stage occurs. For convenience, a stage preceding the first stage will be refereed as a 0-th stage. In other words, the thermometer latch TL0 in the 0-th stage receives the start signal before being delayed and the stop signal before being delayed.
As a result, the output from the thermometer latch TL will be 0 until the stop signal Sstop catches up with the start signal Sstart. Once the stop signal catches up the start signal, the output from the thermometer latch TL0 will be 1. Thus, the data latched by a total of (N+1) thermometer latches TL0-TLN are output as the thermometer code TC [0:N]. The term thermocode derives from the fact that the bit value changes from 1 to 0 (or 0 to 1) at a particular bit in the bit series.
When the stop signal Sstop fails to catch up with the start signal Sstart, all bits of the thermometer code TC will be 0. When the stop signal Sstop is input before the start signal Sstart, all bits will be 1.
[patent document No. 1] U.S. Pat. No. 4,494,021
[patent document No. 2] WO03/36796
In the TDC of FIG. 1, the difference Δt=(t1−t2) between the first predetermined amount t1 and the second predetermined amount t2 in the Vernier delay circuit 200 gives the resolution. Accordingly, there is a problem in that a desired resolution is not achieved when the delay amount provided by the first delay element D1 or the second delay element D2 fluctuates or varies due to fluctuation in the process, temperature, or power supply voltage.
A Vernier delay circuit may be used in applications other than a TDC and it is desirable that the time difference Δt remain constant in other applications as well.